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| STM32F103xC STM32F103xD STM32F103xE High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces Features FBGA Core: ARM 32-bit CortexTM-M3 CPU - 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access - Single-cycle multiplication and hardware division Memories - 256 to 512 Kbytes of Flash memory - up to 64 Kbytes of SRAM - Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories - LCD parallel interface, 8080/6800 modes Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR, and programmable voltage detector (PVD) - 4-to-16 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC with calibration - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers 3 x 12-bit, 1 s A/D converters (up to 21 channels) - Conversion range: 0 to 3.6 V - Triple-sample and hold capability - Temperature sensor 2 x 12-bit D/A converters DMA: 12-channel DMA controller - Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs Debug mode - Serial wire debug (SWD) & JTAG interfaces - Cortex-M3 Embedded Trace MacrocellTM WLCSP64 LQFP64 10 x 10 mm, LQFP100 14 x 14 mm, LQFP144 20 x 20 mm LFBGA100 10 x 10 mm LFBGA144 10 x 10 mm Up to 112 fast I/O ports - 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant Up to 11 timers - Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 2 x 16-bit motor control PWM timers with dead-time generation and emergency stop - 2 x watchdog timers (Independent and Window) - SysTick timer: a 24-bit downcounter - 2 x 16-bit basic timers to drive the DAC Up to 13 communication interfaces - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed - CAN interface (2.0B Active) - USB 2.0 full speed interface - SDIO interface CRC calculation unit, 96-bit unique ID ECOPACK(R) packages Device summary Part number STM32F103RC STM32F103VC STM32F103ZC STM32F103RD STM32F103VD STM32F103ZD STM32F103RE STM32F103ZE STM32F103VE Table 1. Reference STM32F103xC STM32F103xD STM32F103xE September 2009 Doc ID 14611 Rev 7 1/123 www.st.com 1 Contents STM32F103xC, STM32F103xD, STM32F103xE Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2.3.14 2.3.15 2.3.16 2.3.17 2.3.18 2.3.19 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 15 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Universal synchronous/asynchronous receiver transmitters (USARTs) 21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE 2.3.29 2.3.30 Contents Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 4 5 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 5.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43 Embedded reset and power control block characteristics . . . . . . . . . . . 43 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 81 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 97 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Doc ID 14611 Rev 7 3/123 Contents 5.3.20 STM32F103xC, STM32F103xD, STM32F103xE Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115 7 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical current consumption in Sleep mode, coderunning from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 62 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 63 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 76 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 79 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Doc ID 14611 Rev 7 5/123 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. STM32F103xC, STM32F103xD, STM32F103xE I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111 LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 113 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24 STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25 STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26 STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27 STM32F103xC and STM32F103xE performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 46 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 46 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 64 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 65 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 72 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 73 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 75 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 76 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Doc ID 14611 Rev 7 7/123 List of figures Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. STM32F103xC, STM32F103xD, STM32F103xE NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 78 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 79 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 101 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 102 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 106 LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Introduction 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. Doc ID 14611 Rev 7 9/123 Description STM32F103xC, STM32F103xD, STM32F103xE 2 Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM(R) CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xx high-density performance line family operates in the -40 to +105 C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx high-density performance line microcontroller family suitable for a wide range of applications: Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications, PLC, inverters, printers, and scanners Alarm systems, video intercom, and HVAC Figure 1 shows the general block diagram of the device family. 10/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Description 2.1 Device overview Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts STM32F103Rx 256 48 No General-purpose Timers Advanced-control Basic SPI(I2S)(3) I Comm USB CAN SDIO GPIOs 12-bit ADC Number of channels 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures Package 51 3 16 2 2 72 MHz 2.0 to 3.6 V Ambient temperatures: -40 to +85 C /-40 to +105 C (see Table 10) Junction temperature: -40 to + 125 C (see Table 10) LQFP64 WLCSP64 LQFP100, BGA100 LQFP144, BGA144 1 1 1 80 3 16 112 3 21 2C Peripherals Flash memory in Kbytes SRAM in Kbytes FSMC STM32F103Vx 512 256 48 384 64 Yes(2) 4 2 2 3(2) 2 5 512 STM32F103Zx 256 48 Yes 384 64 512 384 64(1) USART 1. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only. 2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 3. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. Doc ID 14611 Rev 7 11/123 Description Figure 1. STM32F103xC, STM32F103xD, STM32F103xE STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram TRACECLK TRACED[0:3] as AS NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF TPIU SW/JTAG Trace/trig Pbus Ibus Cortex-M3 CPU Fmax: 48/72 MHz Dbus System NVIC Bus Matrix POR Reset Int Trace controller Flash obl interface Flash 512 Kbytes 64 bit VDD @VDD Power Volt. reg. 3.3 V to 1.8 V @VDDA Supply supervision POR /PDR PVD @VDD XTAL OSC 4-16 MHz IWDG Standby interface @VBAT XTAL32kHz RTC Backup reg AWU Backup interface AHB2 APB1 TIM2 TIM3 APB1: Fmax = 24/36 MHz TIM4 TIM5 USART2 USART3 UART4 UART5 SPI2 / I2S2 2x(8x16b it) SPI3 / 2x(8x16b I2S3 it) I2C1 SRAM 512 B WWDG I2C2 bxCAN device USB 2.0 FS device TIM6 USBDP/CAN_TX USBDM/CAN_RX VBAT =1.8 V to 3.6 V OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT VSS SRAM 64 KB @V DDA RC 8 MHz RC 40 kHz PLL PCLK1 PCLK2 HCLK FCLK NRST VDDA VSSA GP DMA2 5 channels AHB: Fmax = 48/72 MHz A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL (or NADV) as AF D[7:0] CMD CK as AF GP DMA1 7 channels OSC_IN OSC_OUT FSMC Reset & Clock control SDIO AHB2 APB2 EXT.IT WKUP GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F GPIO port G TIM1 TIM8 SPI1 USART1 Temp. sensor APB2: Fmax = 48/72 MHz 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels as AF RX, TX CTS, RTS, , CK as AF RX, TX, CTS, RTS, CK as AF RX,TX as AF RX,TX as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF 112AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] 4 channels 3 compl. channels BKIN, ETR as AF 4 channels 3 compl. channels BKIN, ETR as AF MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS, CK as AF 8 ADC123_INs common to the 3 ADCs 8 ADC12_INs common to ADC1 & ADC2 5 ADC3_INs on ADC3 VREF- VREF+ 12-bit ADC1 IF 12-bit ADC2 IF 12-bit ADC3 IF @ VDDA TIM7 IF 12bit DAC1 IF 12bit DAC 2 DAC_OUT1 as AF DAC_OUT2 as AF @VDDA ai14666f 1. TA = -40 C to +85 C (suffix 6, see Table 71) or -40 C to +105 C (suffix 7, see Table 71), junction temperature up to 105 C or 125 C, respectively. 2. AF = alternate function on I/O port pin. 12/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Figure 2. Clock tree USB Prescaler /1, 1.5 Description 48 MHz USBCLK to USB interface I2S3CLK Peripheral clock enable to I2S3 I2S2CLK to I2S2 SDIOCLK FSMCCLK to SDIO to FSMC 8 MHz HSI RC HSI Peripheral clock enable Peripheral clock enable /2 Peripheral clock enable 72 MHz max Clock Enable (4 bits) HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock Enable (20 bits) PLLSRC PLLMUL ..., x16 x2, x3, x4 PLL HSI PLLCLK HSE SW SYSCLK /8 72 MHz /1, 2..512 max AHB Prescaler APB1 Prescaler /1, 2, 4, 8, 16 36 MHz max CSS TIM2,3,4,5,6,7 If (APB1 prescaler =1) x1 else x2 to TIM2,3,4,5,6 and 7 TIMXCLK Peripheral Clock Enable (6 bits) PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2 APB2 Prescaler /1, 2, 4, 8, 16 72 MHz max Peripheral Clock Enable (15 bits) PCLK2 peripherals to APB2 TIM1 & 8 timers If (APB2 prescaler =1) x1 else x2 to TIM1 and TIM8 TIMxCLK Peripheral Clock Enable (2 bit) to ADC1, 2 or 3 /128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz LSE to RTC RTCCLK RTCSEL[1:0] ADC Prescaler /2, 4, 6, 8 /2 ADCCLK HCLK/2 LSI RC 40 kHz LSI to Independent Watchdog (IWDG) To SDIO AHB interface Peripheral clock enable IWDGCLK Main Clock Output /2 PLLCLK HSI HSE SYSCLK Legend: HSE = High Speed External clock signal HSI = High Speed Internal clock signal LSI = Low Speed Internal clock signal LSE = Low Speed External clock signal ai14752b MCO MCO 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz, 28 MHz or 56 MHz. Doc ID 14611 Rev 7 13/123 Description STM32F103xC, STM32F103xD, STM32F103xE 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low-density and high-density devices are an extension of the STM32F103x8/B mediumdensity devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC while remaining fully compatible with the other members of the family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Low-density devices 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 48 or 64 KB(2) RAM 384 KB Flash 512 KB Flash Pinout 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 144 100 64 48 36 2 x USARTs 2 x 16-bit timers 1 x SPI, 1 x I2C, USB, CAN, 1 x PWM timer 2 x ADCs 3 x USARTs 3 x 16-bit timers 2 x SPIs, 2 x I2Cs, USB, CAN, 1 x PWM timer 2 x ADCs 64 KB RAM 64 KB RAM 5 x USARTs 4 x 16-bit timers, 2 x basic timers 3 x SPIs, 2 x I2Ss, 2 x I2Cs USB, CAN, 2 x PWM timers 3 x ADCs, 2 x DACs, 1 x SDIO FSMC (100- and 144-pin packages(3)) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. 2. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only. 3. Ports F and G are not available in devices delivered in 100-pin packages. 14/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Description 2.3 2.3.1 Overview ARM(R) CortexTM-M3 core with embedded Flash and SRAM The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory Up to 512 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: The three FSMC interrupt lines are ORed in order to be connected to the NVIC Write FIFO Code execution from external memory except for NAND Flash and PC Card The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz Doc ID 14611 Rev 7 15/123 Description STM32F103xC, STM32F103xD, STM32F103xE 2.3.6 LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 2.3.7 Nested vectored interrupt controller (NVIC) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. 2.3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. 16/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Description 2.3.10 Boot modes At startup, boot pins are used to select one of three boot options: Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. 2.3.11 Power supply schemes VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 12: Power supply scheme. 2.3.12 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.13 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. Doc ID 14611 Rev 7 17/123 Description STM32F103xC, STM32F103xD, STM32F103xE 2.3.14 Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.15 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC. 2.3.16 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a 18/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.17 Timers and watchdogs The high-density STM32F103xx performance line devices include up to two advancedcontrol timers, up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer TIM1, TIM8 TIM2, TIM3, TIM4, TIM5 TIM6, TIM7 High-density timer feature comparison Counter resolution 16-bit Counter type Up, down, up/down Up, down, up/down Prescaler factor Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 DMA request Capture/compare Complementary generation channels outputs Yes 4 Yes 16-bit Yes 4 No 16-bit Up Yes 0 No Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for: Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. Doc ID 14611 Rev 7 19/123 Description STM32F103xC, STM32F103xD, STM32F103xE General-purpose timers (TIMx) There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source 2.3.18 IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 20/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Description 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.20 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.21 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. 2.3.22 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1. 2.3.23 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. Doc ID 14611 Rev 7 21/123 Description STM32F103xC, STM32F103xD, STM32F103xE 2.3.24 Universal serial bus (USB) The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 2.3.25 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 2.3.26 ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.27 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. 22/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE This dual digital Interface supports the following features: Description two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.28 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.29 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.3.30 Embedded Trace MacrocellTM The ARM(R) Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. Doc ID 14611 Rev 7 23/123 Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE 3 Figure 3. 1 Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line BGA144 ballout 2 3 4 5 6 7 8 9 10 11 12 A PC13TAMPER-RTC PE3 PE2 PE1 PE0 PB4 JTRST PB3 JTDO PD6 PD7 PA15 JTDI PA14 JTCK PA13 JTMS B PC14OSC32_IN PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12 C PC15OSC32_OUT VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 NC PA11 D OSC_IN VSS_5 VDD_5 PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E OSC_OUT PF3 PF4 PF5 VSS_3 VSS_11 VSS_10 PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD_4 VDD_3 VDD_11 VDD_10 VDD_8 VDD_2 VDD_9 PC8 PC7 G PF10 PF9 PF8 VSS_4 VDD_6 VDD_7 VDD_1 VSS_8 VSS_2 VSS_9 PG8 PC6 H PC0 PC1 PC2 PC3 VSS_6 VSS_7 VSS_1 PE11 PD11 PG7 PG6 PG5 J VSSA PA0-WKUP PA4 PC4 PB2/ BOOT1 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF- PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 AI14798b 24/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Figure 4. 1 Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line BGA100 ballout 2 3 4 5 6 7 8 9 10 A PC14PC13OSC32_IN TAMPER-RTC PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PC2 PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7 F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6 G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15 H VREF- PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14 J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 AI14601c Doc ID 14611 Rev 7 25/123 Pinouts and pin descriptions Figure 5. STM32F103xC, STM32F103xD, STM32F103xE STM32F103xC and STM32F103xE performance line LQFP144 pinout VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD_2 VSS_2 NC PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_9 VSS_9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD_8 VSS_8 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 VSS_6 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 ai14667 26/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Figure 6. Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line LQFP100 pinout VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai14391 Doc ID 14611 Rev 7 27/123 Pinouts and pin descriptions Figure 7. STM32F103xC, STM32F103xD, STM32F103xE STM32F103xC and STM32F103xE performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14392 28/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Figure 8. Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side 8 7 6 5 4 3 2 1 A VDD_3 VSS_3 BOOT0 PB5 PB3 PD2 PC10 VDD_2 B PC14 PC15 PB9 PB6 PB4 PC11 PA14 BYPASS/ VSS_2 C PC13 NRST VBAT PB7 PC12 PA15 PA12 PA11 D OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9 E PC0 VSSA PA1 PA5 PA8 PC8 PC7 PC6 F PC1 VREF+ PA0WKUP VSS_4 PB1 PB11 PB14 PB15 G VDDA PA3 VDD_4 PA6 PA7 PB10 PB12 PB13 H PA2 PA4 PC4 PC5 PB0 PB2 VSS_1 VDD_1 ai15460b Doc ID 14611 Rev 7 29/123 Pinouts and pin descriptions Table 5. LFBGA144 LFBGA100 STM32F103xC, STM32F103xD, STM32F103xE High-density STM32F103xx pin definitions I / O Level(2) Pins WLCSP64 LQFP100 LQFP144 LQFP64 Pin name Type(1) Alternate functions(4) Main function(3) (after reset) Default Remap A3 A2 A3 B3 - 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PE2 PE3 PE4 PE5 PE6 VBAT I/O I/O I/O I/O I/O S FT FT FT FT FT PE2 PE3 PE4 PE5 PE6 VBAT PC13(6) PC14(6) PC15(6) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA TRACECK/ FSMC_A23 TRACED0/FSMC_A19 TRACED1/FSMC_A20 TRACED2/FSMC_A21 TRACED3/FSMC_A22 B2 C3 B3 D3 B4 E3 C2 B2 C6 A1 B1 A2 C8 A1 B8 PC13-TAMPERI/O RTC(5) PC14OSC32_IN(5) I/O TAMPER-RTC OSC32_IN OSC32_OUT FSMC_A0 FSMC_A1 FSMC_A2 FSMC_A3 FSMC_A4 FSMC_A5 C1 B1 B7 C3 C4 D4 E2 E3 E4 - PC15I/O OSC32_OUT(5) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O I/O I/O I/O I/O I O I/O I/O I/O I/O I/O S D2 C2 D3 D2 F3 F2 G3 G2 G1 - 10 16 11 17 18 19 20 21 22 ADC3_IN4/FSMC_NIORD ADC3_IN5/FSMC_NREG ADC3_IN6/FSMC_NIOWR ADC3_IN7/FSMC_CD ADC3_IN8/FSMC_INTR D1 C1 D8 E1 D1 D7 F1 H1 H2 E1 C7 F1 E8 F2 F8 12 23 13 24 14 25 15 26 16 27 ADC123_IN10 ADC123_IN11 ADC123_IN12 ADC123_IN13 H3 E2 D6 10 17 28 H4 J1 F3 11 18 29 G1 E7 12 19 30 30/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 5. LFBGA144 LFBGA100 Pinouts and pin descriptions High-density STM32F103xx pin definitions (continued) I / O Level(2) Pins WLCSP64 LQFP100 LQFP144 LQFP64 Pin name Type(1) Alternate functions(4) Main function(3) (after reset) Default Remap K1 H1 L1 J1 F7 (7) - 20 31 21 32 VREFVREF+ VDDA S S S VREFVREF+ VDDA WKUP/USART2_CTS(8) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR USART2_RTS(8) ADC123_IN1/ TIM5_CH2/TIM2_CH2(8) USART2_TX(8)/TIM5_CH3 ADC123_IN2/ TIM2_CH3 (8) USART2_RX(8)/TIM5_CH4 ADC123_IN3/TIM2_CH4(8) M1 K1 G8 13 22 33 J2 G2 F6 14 23 34 PA0-WKUP I/O PA0 K2 H2 E6 15 24 35 PA1 I/O PA1 L2 J2 H8 16 25 36 PA2 I/O PA2 M2 K2 G7 17 26 37 G4 E4 F5 18 27 38 F4 J3 F4 G6 19 28 39 G3 H7 20 29 40 PA3 VSS_4 VDD_4 PA4 I/O S S I/O PA3 VSS_4 VDD_4 PA4 SPI1_NSS(8)/ USART2_CK(8) DAC_OUT1/ADC12_IN4 SPI1_SCK(8) DAC_OUT2 ADC12_IN5 SPI1_MISO(8) TIM8_BKIN/ADC12_IN6 TIM3_CH1(8) SPI1_MOSI(8)/ TIM8_CH1N/ADC12_IN7 TIM3_CH2(8) ADC12_IN14 ADC12_IN15 ADC12_IN8/TIM3_CH3 TIM8_CH2N ADC12_IN9/TIM3_CH4(8) TIM8_CH3N TIM1_CH2N TIM1_CH3N TIM1_BKIN K3 H3 E5 21 30 41 PA5 I/O PA5 L3 J3 G5 22 31 42 PA6 I/O PA6 M3 K3 G4 23 32 43 J4 G4 H6 24 33 44 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 I/O I/O I/O I/O I/O PA7 PC4 PC5 PB0 PB1 TIM1_CH1N K4 H4 H5 25 34 45 L4 J4 H4 26 35 46 M4 K4 F4 27 36 47 J5 M5 L5 G5 H3 28 37 48 49 50 I/O FT PB2/BOOT1 I/O FT I/O FT PF11 PF12 FSMC_NIOS16 FSMC_A6 Doc ID 14611 Rev 7 31/123 Pinouts and pin descriptions Table 5. LFBGA144 LFBGA100 STM32F103xC, STM32F103xD, STM32F103xE High-density STM32F103xx pin definitions (continued) I / O Level(2) Pins WLCSP64 LQFP100 LQFP144 LQFP64 Pin name Type(1) Alternate functions(4) Main function(3) (after reset) Default Remap H5 G5 K5 M6 L6 K6 J6 - - - - 51 52 53 54 55 56 57 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK(8)/ TIM1_BKIN(8) SPI2_SCK/I2S2_CK USART3_CTS(8)/ TIM1_CH1N SPI2_MISO/TIM1_CH2N USART3_RTS(8)/ SPI2_MOSI/I2S2_SD TIM1_CH3N(8)/ FSMC_D13 FSMC_D14 USART3_TX USART3_RX FSMC_D7 FSMC_D8 FSMC_D9 FSMC_D10 FSMC_D11 FSMC_D12 I2C2_SCL/USART3_TX(8) I2C2_SDA/USART3_RX(8) TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 TIM2_CH4 FSMC_A7 FSMC_A8 FSMC_A9 FSMC_A10 FSMC_A11 FSMC_D4 FSMC_D5 FSMC_D6 TIM1_ETR TIM1_CH1N TIM1_CH1 M7 H5 L7 K7 H6 G6 J7 J5 K5 G6 38 58 39 59 40 60 61 62 41 63 42 64 43 65 44 66 45 67 46 68 H8 H6 J8 K8 J6 K6 L8 G7 M8 H7 M9 J7 G3 29 47 69 M10 K7 F3 30 48 70 H7 E7 H2 31 49 71 G7 F7 H1 32 50 72 M11 K8 G2 33 51 73 PB12 I/O FT PB12 M12 J8 G1 34 52 74 PB13 I/O FT PB13 L11 H8 F2 35 53 75 L12 G8 F1 36 54 76 L9 K9 K9 J9 55 77 56 78 PB14 PB15 PD8 PD9 I/O FT I/O FT I/O FT I/O FT PB14 PB15 PD8 PD9 32/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 5. LFBGA144 LFBGA100 Pinouts and pin descriptions High-density STM32F103xx pin definitions (continued) I / O Level(2) Pins WLCSP64 LQFP100 LQFP144 LQFP64 Pin name Type(1) Alternate functions(4) Main function(3) (after reset) Default Remap J9 H9 - - 57 79 58 80 59 81 60 82 83 84 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 FSMC_D15 FSMC_A16 FSMC_A17 FSMC_A18 USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2 H9 G9 L10 K10 K10 J10 G8 F8 - K11 H10 K12 G10 J12 J11 J10 H12 H11 H10 G11 G10 F10 - 61 85 62 86 87 88 89 90 91 92 93 94 95 FSMC_D0 FSMC_D1 FSMC_A12 FSMC_A13 FSMC_A14 FSMC_A15 FSMC_INT2 FSMC_INT3 TIM4_CH3 TIM4_CH4 G12 F10 E1 37 63 96 F12 E10 E2 38 64 97 F11 F9 E3 39 65 98 E11 E9 D1 40 66 99 E12 D9 E4 41 67 100 D12 C9 D2 42 68 101 D11 D10 D3 43 69 102 C12 C10 C1 44 70 103 B12 B10 C2 45 71 104 I2S2_MCK/ TIM8_CH1/SDIO_D6 I2S3_MCK/ TIM8_CH2/SDIO_D7 TIM8_CH3/SDIO_D0 TIM8_CH4/SDIO_D1 USART1_CK/ TIM1_CH1(8)/MCO USART1_TX(8)/ TIM1_CH2(8) USART1_RX(8)/ TIM1_CH3(8) USART1_CTS/USBDM CAN_RX(8)/TIM1_CH4(8) USART1_RTS/USBDP/ CAN_TX(8)/TIM1_ETR(8) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 Doc ID 14611 Rev 7 33/123 Pinouts and pin descriptions Table 5. LFBGA144 LFBGA100 STM32F103xC, STM32F103xD, STM32F103xE High-density STM32F103xx pin definitions (continued) I / O Level(2) Pins WLCSP64 LQFP100 LQFP144 LQFP64 Pin name Type(1) Alternate functions(4) Main function(3) (after reset) Default Remap A12 A10 D4 46 72 105 C11 F8 73 106 PA13 I/O FT JTMSSWDIO Not connected PA13 G9 E6 B1 47 74 107 F9 F6 A1 48 75 108 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT VSS_2 VDD_2 JTCKSWCLK JTDI PC10 PC11 PC12 OSC_IN(9) OSC_OUT(9) PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 FSMC_NWAIT FSMC_NE1/FSMC_NCE2 FSMC_NE2/FSMC_NCE3 FSMC_NCE4_1/ FSMC_NE3 FSMC_NCE4_2 FSMC_NE4 FSMC_A24 FSMC_A25 USART2_RX USART2_CK SPI3_NSS/ I2S3_WS UART4_TX/SDIO_D2 UART4_RX/SDIO_D3 UART5_TX/SDIO_CK FSMC_D2(10) FSMC_D3(10) TIM3_ETR/UART5_RX SDIO_CMD FSMC_CLK FSMC_NOE FSMC_NWE USART2_CTS USART2_RTS USART2_TX PA14 TIM2_CH1_ETR PA15 / SPI1_NSS USART3_TX USART3_RX USART3_CK CAN_RX CAN_TX A11 A9 B2 49 76 109 A10 A8 C3 50 77 110 B11 B9 A2 51 78 111 B10 B8 B3 52 79 112 C10 C8 C4 53 80 113 E10 D8 D8 D10 E8 D7 E9 5 6 81 114 82 115 B7 A3 54 83 116 84 117 85 118 86 119 - 120 - 121 87 122 88 123 - 124 - 125 - 126 - 127 - 128 - 129 - 130 - 131 - 132 D9 C7 C9 D7 B9 E7 F7 B6 - A8 C6 A9 D6 E8 D8 C8 B8 D7 C7 E6 F6 B7 - 34/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 5. LFBGA144 LFBGA100 Pinouts and pin descriptions High-density STM32F103xx pin definitions (continued) I / O Level(2) Pins WLCSP64 LQFP100 LQFP144 LQFP64 Pin name Type(1) Alternate functions(4) Main function(3) (after reset) Default Remap A7 A7 A4 55 89 133 PB3/ I/O FT JTDO SPI3_SCK / I2S3_CK/ PB3/TRACESWO TIM2_CH2 / SPI1_SCK PB4 / TIM3_CH1 SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX A6 A6 B4 56 90 134 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 I/O FT I/O I/O FT I/O FT I I/O FT I/O FT I/O FT I/O FT S S NJTRST PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 SPI3_MISO I2C1_SMBA/ SPI3_MOSI I2S3_SD I2C1_SCL(8)/ TIM4_CH1(8) / FSMC_NADV / TIM4_CH2(8) I2C1_SDA(8) B6 C5 A5 57 91 135 C6 B5 B5 58 92 136 D6 A5 C5 59 93 137 D5 D5 A6 60 94 138 C5 B4 D5 61 95 139 B5 A4 B6 62 96 140 97 141 98 142 TIM4_CH3(8)/SDIO_D4 TIM4_CH4(8)/SDIO_D5 TIM4_ETR / FSMC_NBL0 FSMC_NBL1 I2C1_SCL/ CAN_RX I2C1_SDA / CAN_TX A5 D4 A4 C4 E5 F5 E5 A7 63 99 143 F5 A8 64 100 144 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The VREF+ functionality is provided instead. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 10. For devices delivered in LQFP64 packages, the FSMC function is not available. Doc ID 14611 Rev 7 35/123 Pinouts and pin descriptions Table 6. Pins CF PE2 PE3 PE4 PE5 PE6 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 A3 A4 A5 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 A11 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 CF/IDE STM32F103xC, STM32F103xD, STM32F103xE FSMC pin definition FSMC NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM A23 A19 A20 A21 A22 A0 A1 A2 A3 A4 A5 A23 A19 A20 A21 A22 LQFP100 BGA100(1) Yes Yes Yes Yes Yes DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 36/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 6. Pins CF PD9 PD10 PD11 PD12 PD13 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PD0 PD1 PD3 PD4 PD5 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 PB7 PE0 PE1 NCE4_1 NCE4_2 NCE4_1 NCE4_2 NE4 A24 A25 NADV NBL0 NBL1 NE4 A24 A25 NADV NBL0 NBL1 NOE NWE NWAIT NOE NWE NWAIT D2 D3 D2 D3 D2 D3 CLK NOE NWE NWAIT NE1 NE2 NE3 DA2 DA3 CLK NOE NWE NWAIT NE1 NE2 NE3 D0 D1 D0 D1 D14 D15 CF/IDE D14 D15 Pinouts and pin descriptions FSMC pin definition (continued) FSMC NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM D14 D15 A16 A17 A18 D0 D1 A12 A13 A14 A15 INT2 INT3 D2 D3 DA14 DA15 A16 A17 A18 DA0 DA1 D0 D1 D14 D15 CLE ALE LQFP100 BGA100(1) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes NOE NWE NWAIT NCE2 NCE3 Yes Yes Yes Yes Yes Yes Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. Doc ID 14611 Rev 7 37/123 Memory mapping STM32F103xC, STM32F103xD, STM32F103xE 4 Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map Reserved FSMC register FSMC bank4 PCCARD FSMC bank3 NAND (NAND2) FSMC bank2 NAND (NAND1) FSMC bank1 NOR/PSRAM 4 FSMC bank1 NOR/PSRAM 3 FSMC bank1 NOR/PSRAM 2 FSMC bank1 NOR/PSRAM 1 Reserved CRC Reserved Flash interface Reserved RCC Reserved DMA2 DMA1 Reserved SDIO Reserved ADC3 USART1 TIM8 SPI1 TIM1 ADC2 ADC1 Port G Port F Port E Port D Port C Port B Port A EXTI AFIO Reserved DAC PWR BKP Reserved BxCAN Shared USB/CAN SRAM 512 bytes USB registers I2C2 I2C1 UART5 UART4 USART3 USART2 Reserved SPI3/I2 S3 0xA000 1000 - 0xBFFF FFFF 0xA000 0000 - 0xA000 0FFF 0x9000 0000 - 0x9FFF FFFF 0x8000 0000 - 0x8FFF FFFF 0x7000 0000 - 0x7FFF FFFF 0x6C00 0000 - 0x6FFF FFFF 0x6800 0000 - 0x6BFF FFFF 0x6400 0000 - 0x67FF FFFF 0x6000 0000 - 0x63FF FFFF 0x4002 4400 - 0x5FFF FFFF 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0400 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF 0x4001 400 - 0x4001 7FFF 0x4001 3C00 - 0x4001 3FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF 0x4000 6000 - 0x4000 63FF 0x4000 5C00 - 0x4000 5FFF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 1800 - 0x4000 27FF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC register 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 Reserved SRAM (64 KB aliased by bit-banding) Option Bytes System memory Reserved Flash Reserved Aliased to Flash or system memory depending on BOOT pins 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF SPI2/I2S2 Reserved IWDG WWDG RTC Reserved TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF F80F 0x1FFF F000- 0x1FFF F7FF 0x1FFF EFFF 0x0808 0000 0x0807 FFFF 0x0800 0000 0x07FF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000 ai14753d 38/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5 5.1 Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage STM32F103xx pin C = 50 pF VIN STM32F103xx pin ai14141 ai14142 Doc ID 14611 Rev 7 39/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.1.6 Power supply scheme Figure 12. Power supply scheme VBAT 1.8-3.6V Po wer swi tch Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT Level shifter GP I/Os IN IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD1/2/.../11 Regulator 11 x 100 nF + 1 x 4.7 F VSS1/2/.../11 VDD VREF VDDA VREF+ VREFVSSA ai15401 10 nF + 1 F 10 nF + 1 F ADC Analog: RCs, PLL, ... Caution: In Figure 12, the 4.7 F capacitor must be connected to VDD3. 5.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 40/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Symbol VDD-VSS VIN |VDDx| |VSSX VSS| VESD(HBM) Voltage characteristics Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min -0.3 VSS 0.3 VSS 0.3 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) V Unit 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 8: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VINmax while a negative injection is induced by VIN < VSS. Table 8. Symbol IVDD IVSS IIO Current characteristics Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink)(1) Max. 150 150 25 25 mA Injected current on NRST pin 5 5 5 25 Unit Output current sunk by any I/O and control pin Output current source by any I/Os and control pin IINJ(PIN) (2)(3) IINJ(PIN)(2) Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin(4) Total injected current (sum of all I/O and control pins)(4) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Doc ID 14611 Rev 7 41/123 Electrical characteristics Table 9. Thermal characteristics STM32F103xC, STM32F103xD, STM32F103xE Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Value -65 to +150 150 Unit C C 5.3 5.3.1 Operating conditions General operating conditions Table 10. Symbol fHCLK fPCLK1 fPCLK2 VDD General operating conditions Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage LQFP144 Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(3) LQFP100 LQFP64 LFBGA100 LFBGA144 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation(4) Maximum power dissipation Low power dissipation 6 suffix version (4) Conditions Min 0 0 0 2 2 Max 72 36 72 3.6 3.6 Unit MHz V VDDA (1) Must be the same potential as VDD(2) V 2.4 1.8 3.6 3.6 666 434 444 500 500 -40 -40 -40 -40 -40 -40 85 C 105 105 C 125 105 C 125 mW V VBAT PD TA Ambient temperature for 7 suffix version TJ Junction temperature range 7 suffix version 1. When the ADC is used, refer to Table 58: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 114). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 114). 42/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.2 Operating conditions at power-up / power-down The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10. Table 11. Symbol tVDD Operating conditions at power-up / power-down Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit s/V 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 12. Symbol Embedded reset and power control block characteristics Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.88 1.84 1.92 40 1 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV mS VPVD Programmable voltage detector level selection PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge) VPVDhyst(2) VPOR/PDR VPDRhyst (2) (2) PVD hysteresis Power on/power down reset threshold PDR hysteresis Reset temporization TRSTTEMPO 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. Doc ID 14611 Rev 7 43/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.4 Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions -40 C < TA < +105 C -40 C < TA < +85 C Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1(2) Unit V V s ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) Temperature coefficient VDD = 3 V 10 mV 10 100 mV ppm/C 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 13: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 14, Table 15 and Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. 44/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 14. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 69 50 39 27 20 11 37 28 22 16.5 12.5 8 TA = 105 C 70 50.5 39.5 28 20.5 11.5 37.5 28.5 22.5 17 13 8 mA Symbol IDD Supply current in Run mode 8 MHz 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 15. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 66 43.5 33 23 16 9 33 23 18 13 10 6 TA = 105 C 67 45.5 35 24.5 18 10.5 33.5 23.5 18.5 13.5 10.5 6.5 mA Symbol IDD Supply current in Run mode 8 MHz 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 1. Data based on characterization results, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 14611 Rev 7 45/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 70 60 50 Consumption (mA) 40 30 20 10 0 -45 25 70 Temperature (C) 85 105 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled 35 30 25 Consumption (mA) 20 15 10 5 0 -45 25 70 Temperature (C) 85 105 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz 46/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 16. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Parameter Conditions fHCLK TA = 85 C 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz 45 31 24 17 12.5 8 8.5 7 6 5 4.5 4 TA = 105 C 46 32 25 17.5 13 8 mA 72 MHz 48 MHz External clock(2), all peripherals disabled 36 MHz 24 MHz 16 MHz 8 MHz 9 7.5 6.5 5.5 5 4 Unit Symbol IDD Supply current in Sleep mode 8 MHz 1. Based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 14611 Rev 7 47/123 Electrical characteristics Table 17. Symbol STM32F103xC, STM32F103xD, STM32F103xE Typical and maximum current consumptions in Stop and Standby modes Typ(1) Parameter Conditions Max Unit VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = = 2.0 V = 2.4 V = 3.3 V 85 C 105 C Regulator in run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current in OFF (no independent watchdog) Stop mode Regulator in low-power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator Supply current in ON, independent watchdog OFF Standby mode Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF IDD_VBAT Backup domain Low-speed oscillator and RTC ON supply current 1.05 34.5 35 379 1130 24.5 25 365 1110 IDD 3 2.8 3.8 3.6 5(2) 2(2) 6.5(2) 2.3(2) A 1.9 2.1 1.1 1.4 1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production. Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values 2.5 2 Consumption (A) 1.8 V 1.5 2V 2.4 V 3.3 V 3.6 V 1 0.5 0 -45 25 Temperature (C) 85 105 ai17337 48/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values 700 600 500 Consumption (A) 400 300 200 2.4V 2.7V 3.0V 3.3V 3.6V -45 25 70 Temperature (C) 85 105 100 0 Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values 700 600 500 Consumption (A) 400 300 200 2.4V 2.7V 3.0V 3.3V 3.6V -45 25 70 Temperature (C) 85 105 100 0 Doc ID 14611 Rev 7 49/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values 4.5 4 3.5 Consumption (A) 3 2.5 2 1.5 1 0.5 0 -45 25 70 Temperature (C) 85 105 2.4V 2.7V 3.0V 3.3V 3.6V Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 10. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 50/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 18. Electrical characteristics Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Parameter Conditions fHCLK 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) Symbol All peripherals All peripherals disabled enabled(2) 51 34.6 26.6 18.5 12.8 7.2 4.2 2.7 2 1.6 1.3 45 34 26 17.9 12.2 6.6 3.6 2.1 1.4 1 0.7 30.5 20.7 16.2 11.4 8.2 5 3.1 2.1 1.7 1.4 1.2 27 20.1 15.6 10.8 7.6 4.4 2.5 1.5 1.1 0.8 0.6 Unit 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz mA IDD Supply current in Run mode 125 kHz 64 MHz 48 MHz 36 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz mA 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 14611 Rev 7 51/123 Electrical characteristics Table 19. STM32F103xC, STM32F103xD, STM32F103xE Typical current consumption in Sleep mode, coderunning from Flash or RAM Typ(1) Conditions fHCLK Unit Symbol Parameter All peripherals All peripherals enabled(2) disabled 29.5 20 15.1 10.4 7.2 3.9 2.6 1.85 1.5 1.3 1.2 25.6 19.4 14.5 9.8 6.6 3.3 2 1.25 0.9 0.7 0.6 6.4 4.6 3.6 2.6 2 1.3 1.2 1.15 1.1 1.05 1.05 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Sleep mode 125 kHz 64 MHz 48 MHz 36 MHz 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 1 MHz 500 kHz 125 kHz mA 5.1 4 3 2 1.4 0.7 0.6 0.55 0.5 0.45 0.45 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 52/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - - with all peripherals clocked off with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 7 Peripheral current consumption(1) Peripheral TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 SPI2 SPI3 Table 20. Typical consumption at 25 C 1.2 1.2 1.2 1.2 0.4 0.4 0.2 0.2 0.4 0.4 0.5 0.6 0.4 0.4 0.65 0.72 0.72 Unit APB1 USART2 USART3 UART4 UART5 I2C1 I2C2 USB CAN DAC mA Doc ID 14611 Rev 7 53/123 Electrical characteristics Table 20. STM32F103xC, STM32F103xD, STM32F103xE Peripheral current consumption(1) (continued) Peripheral GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF Typical consumption at 25 C 0.55 0.72 0.72 0.55 1 0.72 1 1.9 1.7 1.8 0.4 1.7 0.9 1.7 Unit APB2 GPIOG ADC1(2) ADC2 TIM1 SPI1 TIM8 USART1 ADC3 mA 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 21. Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) High-speed external user clock characteristics Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) 5 45 VSS VIN VDD 55 1 Conditions Min 1 0.7VDD VSS 16 ns 20 pF % A Typ 8 Max 25 VDD 0.3VDD Unit MHz V OSC_IN input capacitance(1) DuCy(HSE) Duty cycle IL OSC_IN Input leakage current 1. Guaranteed by design, not tested in production. 54/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in Table 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 22. Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE) Low-speed external user clock characteristics Parameter User External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) 5 30 VSS VIN VD D Conditions Min Typ 32.768 Max 1000 VDD Unit kHz 0.7VDD VSS 450 V 0.3VDD ns 50 pF 70 1 % A OSC32_IN input capacitance(1) DuCy(LSE) Duty cycle IL OSC32_IN Input leakage current 1. Guaranteed by design, not tested in production. Figure 20. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Doc ID 14611 Rev 7 55/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 21. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t EXTER NAL CLOCK SOURC E fLSE_ext OSC32_IN IL STM32F103xx ai14144b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. Symbol fOSC_IN RF C HSE 4-16 MHz oscillator characteristics(1)(2) Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) HSE driving current Oscillator transconductance Startup time RS = 30 VDD= 3.3 V, VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz k pF i2 gm tSU(HSE)(4) 1 mA mA/V ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 22). CL1 and CL2 are usually the 56/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 22. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator REXT(1) OSC_OU T RF Bias controlled gain STM32F103xx ai14145 fHSE CL2 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 24. Symbol RF C(2) I2 gm tSU(LSE) (4) LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator transconductance Startup time VDD is stabilized RS = 30 k VDD = 3.3 V, VIN = VSS 5 3 Conditions Min Typ 5 15 1.4 Max Unit M pF A A/V s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Doc ID 14611 Rev 7 57/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 23. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN 32.768 kH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F103xx fLSE ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25. Symbol fHSI HSI oscillator characteristics(1) Parameter Frequency User-trimmed with the RCC_CR register(2) Conditions Min Typ 8 1(3) -2 -1.5 -1.3 -1.1 1 80 2.5 2.2 2 1.8 2 100 Max Unit MHz % % % % % s A ACCHSI Accuracy of the HSI oscillator Factorycalibrated(4) TA = -40 to 105 C TA = -10 to 85 C TA = 0 to 70 C TA = 25 C tsu(HSI)(4) IDD(HSI)(4) HSI oscillator startup time HSI oscillator power consumption 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. 58/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed internal (LSI) RC oscillator Table 26. Symbol fLSI(2) tsu(LSI)(3) IDD(LSI)(3) Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 LSI oscillator characteristics (1) Parameter Min 30 Typ 40 Max 60 85 1.2 Unit kHz s A 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 27. Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Low-power mode wakeup timings Parameter Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) Wakeup from Stop mode (regulator in low power mode) Wakeup from Standby mode Typ 1.8 3.6 s 5.4 50 s Unit s 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. Doc ID 14611 Rev 7 59/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.8 PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. Symbol PLL characteristics Value Parameter Min PLL input clock(2) 1 40 16 Typ 8.0 Max(1) 25 60 72 200 300 Unit MHz % MHz s ps fPLL_IN fPLL_OUT tLOCK Jitter PLL input clock duty cycle PLL multiplier output clock PLL lock time Cycle-to-cycle jitter 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 29. Symbol tprog tERASE tME Flash memory characteristics Parameter Conditions Min 40 20 20 Typ 52.5 Max(1) 70 40 40 28 Unit s ms ms mA 16-bit programming time TA-40 to +105 C Page (2 KB) erase time Mass erase time TA -40 to +105 C TA -40 to +105 C Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V IDD Supply current Write mode fHCLK = 72 MHz, VDD = 3.3 V Erase mode fHCLK = 72 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V 7 5 50 2 3.6 mA mA A V Vprog Programming voltage 1. Guaranteed by design, not tested in production. 60/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 30. Symbol Electrical characteristics Flash memory endurance and data retention Value Parameter Conditions TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 1 kcycle(2) at TA = 85 C (2) Min(1) 10 30 10 20 Unit Typ Max kcycles NEND Endurance tRET Data retention 1 kcycle at TA = 105 C (2) Years 10 kcycles at TA = 55 C 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous waveforms and timings Figure 24 through Figure 27 represent asynchronous waveforms and Table 31 through Table 34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: AddressSetupTime = 0 AddressHoldTime = 1 DataSetupTime = 1 Doc ID 14611 Rev 7 61/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FSMC_NOE FSMC_NWE tv(A_NE) FSMC_A[25:0] Address t h(A_NOE) tv(BL_NE) FSMC_NBL[1:0] t h(BL_NOE) t h(Data_NE) t su(Data_NOE) t su(Data_NE) th(Data_NOE) FSMC_D[15:0] t v(NADV_NE) tw(NADV) Data FSMC_NADV(1) ai14991B 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(A_NOE) tv(BL_NE) th(BL_NOE) tsu(Data_NE) th(Data_NOE) th(Data_NE) tv(NADV_NE) tw(NADV) 1. CL = 15 pF. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time Min 5THCLK - 1.5 0.5 5THCLK - 1.5 Max 5THCLK + 2 1.5 5THCLK + 1.5 7 0.1 0 0 2THCLK + 25 2THCLK + 25 0 0 5 THCLK + 1.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns FSMC_NOE high to FSMC_NE high hold time -1.5 FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NOE high Data to FSMC_NEx high setup time tsu(Data_NOE) Data to FSMC_NOEx high setup time Data hold time after FSMC_NOE high Data hold time after FSMC_NEx high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time 2. Based on characterization, not tested in production. 62/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] Address th(A_NWE) tv(BL_NE) FSMC_NBL[1:0] tv(Data_NE) NBL th(BL_NWE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 32. Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) th(A_NWE) tv(BL_NE) th(BL_NWE) tv(Data_NE) th(Data_NWE) tv(NADV_NE) tw(NADV) 1. CL = 15 pF. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high FSMC_NEx low to Data valid Data hold time after FSMC_NWE high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time THCLK 5.5 THCLK + 1.5 THCLK - 0.5 THCLK + 7 THCLK 1.5 Min 3THCLK - 1 THCLK - 0.5 THCLK - 0.5 THCLK 7.5 Max 3THCLK + 2 THCLK + 1.5 THCLK + 1.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2. Based on characterization, not tested in production. Doc ID 14611 Rev 7 63/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] Address t h(A_NOE) tv(BL_NE) FSMC_NBL[1:0] NBL th(BL_NOE) th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Data th(Data_NOE) FSMC_AD[15:0] Address t v(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NADV ai14892b Table 33. Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) th(A_NOE) th(BL_NOE) tv(BL_NE) tsu(Data_NE) th(Data_NE) th(Data_NOE) 1. CL = 15 pF. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NOE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high Address hold time after FSMC_NOE high FSMC_BL hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid Data to FSMC_NEx high setup time 2THCLK + 24 2THCLK + 25 0 0 3 THCLK -1.5 THCLK THCLK 0 0 Min 7THCLK - 2 4THCLK - 1 -1 0 5 THCLK + 1.5 Max 7THCLK + 2 4THCLK + 2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3THCLK - 0.5 3THCLK + 1.5 tsu(Data_NOE) Data to FSMC_NOE high setup time Data hold time after FSMC_NEx high Data hold time after FSMC_NOE high 2. Based on characterization, not tested in production. 64/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] Address th(A_NWE) tv(BL_NE) FSMC_NBL[1:0] t v(A_NE) NBL th(BL_NWE) t v(Data_NADV) Data th(Data_NWE) FSMC_AD[15:0] Address t v(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NADV ai14891B Table 34. Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) th(A_NWE) tv(BL_NE) th(BL_NWE) Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high THCLK - 1.5 THCLK + 1.5 THCLK - 5 3 THCLK - 1 THCLK - 3 4THCLK 1.6 Min 5THCLK - 1 2THCLK 2THCLK - 1 THCLK - 1 7 5 THCLK + 1 Max 5THCLK + 2 2THCLK + 1 2THCLK + 2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) 1. CL = 15 pF. 2. Based on characterization, not tested in production. Data hold time after FSMC_NWE high Doc ID 14611 Rev 7 65/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Synchronous waveforms and timings Figure 28 through Figure 31 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: BurstAccessMode = FSMC_BurstAccessMode_Enable; MemoryType = FSMC_MemoryType_CRAM; WriteBurst = FSMC_WriteBurst_Enable; CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual) DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 28. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) FSMC_CLK Data latency = 1 td(CLKL-NExL) FSMC_NEx td(CLKL-NADVL) FSMC_NADV td(CLKL-AV) FSMC_A[25:16] td(CLKL-NOEL) FSMC_NOE td(CLKL-ADIV) td(CLKL-ADV) FSMC_AD[15:0] AD[15:0] tsu(NWAITV-CLKH) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893e tw(CLK) BUSTURN = 0 td(CLKH-NExH) td(CLKL-NADVH) td(CLKH-AIV) td(CLKH-NOEH) th(CLKH-ADV) tsu(ADV-CLKH) D1 D2 th(CLKH-NWAITV) th(CLKH-ADV) tsu(ADV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) 66/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 35. Symbol tw(CLK) td(CLKL-NExL) td(CLKH-NExH) td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV) td(CLKL-NOEL) td(CLKH-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16...25) 5 Electrical characteristics Synchronous multiplexed NOR/PSRAM read timings(1)(2) Parameter Min 27.7 1.5 THCLK + 2 4 Max Unit ns ns ns ns ns 0 ns ns THCLK +1 THCLK + 0.5 12 0 6 ns ns ns ns ns ns ns ns FSMC_CLK high to FSMC_Ax invalid (x = 16...25) THCLK + 2 FSMC_CLK low to FSMC_NOE low FSMC_CLK high to FSMC_NOE high FSMC_CLK low to FSMC_AD[15:0] valid FSMC_CLK low to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid data before FSMC_CLK high FSMC_A/D[15:0] valid data after FSMC_CLK high THCLK - 10 8 2 tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) 1. CL = 15 pF. 2. Based on characterization, not tested in production. FSMC_NWAIT valid after FSMC_CLK high Doc ID 14611 Rev 7 67/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 29. Synchronous multiplexed PSRAM write timings tw(CLK) FSMC_CLK Data latency = 1 td(CLKL-NExL) FSMC_NEx td(CLKL-NADVL) FSMC_NADV td(CLKL-AV) FSMC_A[25:16] td(CLKL-NWEL) FSMC_NWE td(CLKL-ADIV) td(CLKL-ADV) FSMC_AD[15:0] AD[15:0] td(CLKL-Data) D1 D2 td(CLKL-Data) td(CLKH-NWEH) td(CLKH-AIV) td(CLKL-NADVH) tw(CLK) BUSTURN = 0 td(CLKH-NExH) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH) FSMC_NBL ai14992d 68/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 36. Symbol tw(CLK) td(CLKL-NExL) td(CLKH-NExH) td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV) td(CLKL-NWEL) td(CLKH-NWEH) td(CLKL-ADV) td(CLKL-ADIV) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH) 1. CL = 15 pF. 2. Based on characterization, not tested in production. Electrical characteristics Synchronous multiplexed PSRAM write timings(1)(2) Parameter FSMC_CLK period FSMC_CLK low to FSMC_Nex low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16...25) FSMC_CLK high to FSMC_Ax invalid (x = 16...25) FSMC_CLK low to FSMC_NWE low FSMC_CLK high to FSMC_NWE high FSMC_CLK low to FSMC_AD[15:0] valid FSMC_CLK low to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid after FSMC_CLK low FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high FSMC_CLK low to FSMC_NBL high 7 2 1 3 6 THCLK +1 12 TCK + 2 1 5 0 THCLK + 2 4 Min 27.7 2 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Doc ID 14611 Rev 7 69/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) FSMC_CLK td(CLKL-NExL) FSMC_NEx td(CLKL-NADVL) FSMC_NADV td(CLKL-AV) FSMC_A[25:0] td(CLKL-NOEL) FSMC_NOE tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) FSMC_D[15:0] tsu(NWAITV-CLKH) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894d tw(CLK) BUSTURN = 0 Data latency = 1 td(CLKH-NExH) td(CLKL-NADVH) td(CLKH-AIV) td(CLKH-NOEH) th(CLKH-DV) D2 D1 th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) Table 37. Symbol tw(CLK) td(CLKL-NExL) td(CLKH-NExH) td(CLKL-NADVL) Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 0...25) FSMC_CLK high to FSMC_Ax invalid (x = 0...25) THCLK + 4 FSMC_CLK low to FSMC_NOE low FSMC_CLK high to FSMC_NOE high THCLK + 1.5 5 0 THCLK + 2 4 Min 27.7 1.5 Max Unit ns ns ns ns ns ns ns THCLK + 1.5 ns ns ns ns ns ns td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV) td(CLKL-NOEL) td(CLKH-NOEH) tsu(DV-CLKH) th(CLKH-DV) FSMC_D[15:0] valid data before FSMC_CLK high 6.5 FSMC_D[15:0] valid data after FSMC_CLK high 7 7 2 tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high th(CLKH-NWAITV) 1. CL = 15 pF. 2. Based on characterization, not tested in production. FSMC_NWAIT valid after FSMC_CLK high 70/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 31. Synchronous non-multiplexed PSRAM write timings tw(CLK) FSMC_CLK td(CLKL-NExL) FSMC_NEx td(CLKL-NADVL) FSMC_NADV td(CLKL-AV) FSMC_A[25:0] td(CLKL-NWEL) FSMC_NWE td(CLKL-Data) FSMC_D[15:0] D1 td(CLKL-Data) D2 td(CLKH-NWEH) td(CLKH-AIV) td(CLKL-NADVH) Data latency = 1 td(CLKH-NExH) tw(CLK) BUSTURN = 0 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKL-NBLH) th(CLKH-NWAITV) FSMC_NBL ai14993e Table 38. Symbol tw(CLK) td(CLKL-NExL) td(CLKH-NExH) Synchronous non-multiplexed PSRAM write timings(1)(2) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16...25) FSMC_CLK high to FSMC_Ax invalid (x = 16...25) FSMC_CLK low to FSMC_NWE low FSMC_CLK high to FSMC_NWE high FSMC_D[15:0] valid data after FSMC_CLK low FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high FSMC_CLK low to FSMC_NBL high 7 2 1 THCLK + 1 6 TCK + 2 1 5 0 THCLK + 2 4 Min 27.7 2 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV) td(CLKL-NWEL) td(CLKH-NWEH) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH) 1. CL = 15 pF. 2. Based on characterization, not tested in production. Doc ID 14611 Rev 7 71/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE PC Card/CompactFlash controller waveforms and timings Figure 32 through Figure 37 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: COM.FSMC_SetupTime = 0x04; COM.FSMC_WaitSetupTime = 0x07; COM.FSMC_HoldSetupTime = 0x04; COM.FSMC_HiZSetupTime = 0x00; ATT.FSMC_SetupTime = 0x04; ATT.FSMC_WaitSetupTime = 0x07; ATT.FSMC_HoldSetupTime = 0x04; ATT.FSMC_HiZSetupTime = 0x00; IO.FSMC_SetupTime = 0x04; IO.FSMC_WaitSetupTime = 0x07; IO.FSMC_HoldSetupTime = 0x04; IO.FSMC_HiZSetupTime = 0x00; TCLRSetupTime = 0; TARSetupTime = 0; Figure 32. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 tv(NCEx-A) FSMC_A[10:0] td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) th(NCEx-AI) FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tsu(D-NOE) FSMC_D[15:0] ai14895b th(NOE-D) tw(NOE) 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. 72/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 33. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NREG-NCE4_1) td(NIORD-NCE4_1) FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NWE) FSMC_NWE tw(NWE) td(NWE-NCE4_1) FSMC_NOE MEMxHIZ =1 td(D-NWE) tv(NWE-D) FSMC_D[15:0] th(NWE-D) ai14896b Doc ID 14611 Rev 7 73/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 High th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) FSMC_NREG th(NCE4_1-NREG) FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tsu(D-NOE) FSMC_D[15:0](1) ai14897b tw(NOE) td(NOE-NCE4_1) th(NOE-D) 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 74/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) FSMC_NREG td(NCE4_1-NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) tw(NWE) th(NCE4_1-NREG) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access FSMC_NCE4_1 FSMC_NCE4_2 tv(NCEx-A) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE th(NCE4_1-AI) FSMC_NIOWR td(NIORD-NCE4_1) FSMC_NIORD tsu(D-NIORD) FSMC_D[15:0] ai14899B tw(NIORD) td(NIORD-D) Doc ID 14611 Rev 7 75/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 tv(NCEx-A) FSMC_A[10:0] th(NCE4_1-AI) FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) FSMC_NIOWR ATTxHIZ =1 tv(NIOWR-D) FSMC_D[15:0] ai14900b tw(NIOWR) th(NIOWR-D) Table 39. Symbol tv(NCEx-A) tv(NCE4_1-A) th(NCEx-AI) th(NCE4_1-AI) Switching characteristics for PC Card/CF read and write cycles(1)(2) Parameter FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 THCLK + 3 high to FSMC_NREG invalid FSMC_NCE4_1 low to FSMC_NOE low FSMC_NOE low width FSMC_NOE high to FSMC_NCE4_1 high FSMC_D[15:0] valid data before FSMC_NOE high FSMC_D[15:0] valid data after FSMC_NOE high FSMC_NWE low width FSMC_NWE high to FSMC_NCE4_1 high FSMC_NCE4_1 low to FSMC_NWE low FSMC_NWE low to FSMC_D[15:0] valid FSMC_NWE high to FSMC_D[15:0] invalid FSMC_D[15:0] valid before FSMC_NWE high 11THCLK 13THCLK 5THCLK + 2 8THCLK -1.5 8THCLK + 1 5THCLK + 2 25 15 8THCLK - 1 5THCLK + 2 5THCLK + 1.5 0 8THCLK + 2 2.5 Min 0 Max Unit ns ns td(NREG-NCEx) td(NREG-NCE4_1) th(NCEx-NREG) th(NCE4_1-NREG) td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1 tsu(D-NOE) th(NOE-D) tw(NWE) td(NWE-NCE4_1) td(NCE4_1-NWE) tv(NWE-D) th(NWE-D) td(D-NWE) 5 ns ns ns ns ns ns ns ns ns ns ns ns ns 76/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 39. Symbol tw(NIOWR) tv(NIOWR-D) th(NIOWR-D) Electrical characteristics Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued) Parameter FSMC_NIOWR low width FSMC_NIOWR low to FSMC_D[15:0] valid FSMC_NIOWR high to FSMC_D[15:0] invalid 11THCLK 5THCLK+3ns 5THCLK - 5 5THCLK + 2.5 5THCLK - 5 4.5 9 8THCLK + 2 Min 8THCLK + 3 5THCLK +1 Max Unit ns ns ns ns ns ns ns ns ns ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid th(NCE4_1-NIOWR) FSMC_NCE4_1 high to FSMC_NIOWR invalid td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 td(NIORD-NCE4_1) low to FSMC_NIORD valid th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD invalid th(NCE4_1-NIORD) FSMC_NCE4_1 high to FSMC_NIORD invalid tsu(D-NIORD) td(NIORD-D) tw(NIORD) 1. CL = 15 pF. 2. Based on characterization, not tested in production. FSMC_D[15:0] valid before FSMC_NIORD high FSMC_D[15:0] valid after FSMC_NIORD high FSMC_NIORD low width NAND controller waveforms and timings Figure 38 through Figure 41 represent synchronous waveforms and Table 40 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: COM.FSMC_SetupTime = 0x01; COM.FSMC_WaitSetupTime = 0x03; COM.FSMC_HoldSetupTime = 0x02; COM.FSMC_HiZSetupTime = 0x01; ATT.FSMC_SetupTime = 0x01; ATT.FSMC_WaitSetupTime = 0x03; ATT.FSMC_HoldSetupTime = 0x02; ATT.FSMC_HiZSetupTime = 0x01; Bank = FSMC_Bank_NAND; MemoryDataWidth = FSMC_MemoryDataWidth_16b; ECC = FSMC_ECC_Enable; ECCPageSize = FSMC_ECCPageSize_512Bytes; TCLRSetupTime = 0; TARSetupTime = 0; Doc ID 14611 Rev 7 77/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 38. NAND controller waveforms for read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) FSMC_NOE (NRE) tsu(D-NOE) FSMC_D[15:0] th(NOE-D) th(NOE-ALE) ai14901b Figure 39. NAND controller waveforms for write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) FSMC_NWE th(NWE-ALE) FSMC_NOE (NRE) tv(NWE-D) FSMC_D[15:0] th(NWE-D) ai14902b Figure 40. NAND controller waveforms for common memory read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) FSMC_D[15:0] th(NOE-D) th(NOE-ALE) ai14912b 78/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 41. NAND controller waveforms for common memory write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) FSMC_NWE tw(NWE) th(NOE-ALE) FSMC_NOE td(D-NWE) tv(NWE-D) FSMC_D[15:0] th(NWE-D) ai14913b Table 40. Symbol td(D-NWE)(2) tw(NOE) (2) Switching characteristics for NAND Flash read and write cycles(1) Parameter FSMC_D[15:0] valid before FSMC_NWE high FSMC_NOE low width FSMC_D[15:0] valid data before FSMC_NOE high Min 6THCLK + 12 4THCLK - 1.5 4THCLK + 1.5 25 Max Unit ns ns ns ns 4THCLK + 2.5 0 10THCLK + 4 3THCLK + 1.5 3THCLK + 4.5 3THCLK + 2 3THCLK + 4.5 ns ns ns ns ns ns ns tsu(D-NOE)(2) th(NOE-D)(2) tw(NWE) (2) FSMC_D[15:0] valid data after FSMC_NOE high 7 FSMC_NWE low width FSMC_NWE low to FSMC_D[15:0] valid FSMC_NWE high to FSMC_D[15:0] invalid FSMC_ALE valid before FSMC_NWE low FSMC_NWE high to FSMC_ALE invalid 4THCLK - 1 tv(NWE-D)(2) th(NWE-D)(2) td(ALE-NWE)(3) th(NWE-ALE)(3) th(NOE-ALE)(3) 1. CL = 15 pF. td(ALE-NOE)(3) FSMC_ALE valid before FSMC_NOE low FSMC_NWE high to FSMC_ALE invalid 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Doc ID 14611 Rev 7 79/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. Symbol EMS characteristics Parameter Conditions Level/ Class 2B VFESD VDD 3.3 V, LQFP144, TA +25 C, Voltage limits to be applied on any I/O pin to fHCLK 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, LQFP144, TA +25 C, fHCLK 72 MHz conforms to IEC 61000-4-4 VEFTB 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) 80/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Prequalification trials Electrical characteristics Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 42. Symbol EMI characteristics Parameter Conditions Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 8 31 28 4 12 21 33 4 dBV SEMI Peak level 0.1 to 30 MHz VDD 3.3 V, TA 25 C, 30 to 130 MHz LQFP144 package compliant with IEC 130 MHz to 1GHz 61967-2 SAE EMI Level 5.3.12 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 43. Symbol VESD(HBM) ESD absolute maximum ratings Ratings Conditions Class Maximum value(1) Unit 2000 V 500 Electrostatic discharge TA +25 C, conforming 2 voltage (human body model) to JESD22-A114 Electrostatic discharge TA +25 C, conforming II VESD(CDM) voltage (charge device model) to JESD22-C101 1. Based on characterization results, not tested in production. Doc ID 14611 Rev 7 81/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 44. Symbol LU Electrical sensitivities Parameter Static latch-up class Conditions TA +105 C conforming to JESD78A Class II level A 5.3.13 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 45. Symbol VIL VIH VIL VIH I/O static characteristics Parameter Input low level voltage Standard IO input high level voltage IO FT(1) input high level voltage Input low level voltage CMOS ports Input high level voltage Standard IO Schmitt trigger voltage hysteresis(2) 0.65 VDD 200 5% VDD(3) VSS VIN VDD Standard I/Os VIN= 5 V, I/O FT 1 A 3 30 30 40 40 5 50 50 k k pF TTL ports Conditions Min -0.5 2 2 -0.5 Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV V Unit Vhys IO FT Schmitt trigger voltage hysteresis(2) Input leakage current (4) resistor(5) resistor(5) Ilkg RPU RPD CIO Weak pull-up equivalent VIN VSS VIN VDD Weak pull-down equivalent I/O pin capacitance 1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 82/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: For VIH: - - if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included For VIL: - - Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). Output voltage levels Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Doc ID 14611 Rev 7 83/123 Electrical characteristics Table 46. Symbol VOL(1) VOH(2) VOL (1) VOH (2) VOL(1)(3) VOH(2)(3) VOL(1)(3) VOH(2)(3) STM32F103xC, STM32F103xD, STM32F103xE Output voltage characteristics Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 Unit IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. 84/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 42 and Table 47, respectively. Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 47. I/O AC characteristics(1) Parameter Conditions Min Max 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125(3) 10 25(3) CL = 50 pF, VDD = 2 V to 3.6 V 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V 11 tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V tr(IO)out Output low to high level rise time Pulse width of external signals detected by the EXTI controller CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V 50 30 20 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) ns MHz MHz MHz ns MHz ns Unit MHz MODEx[1:0] Symbol bit value(1) fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time - tEXTIpw 10 ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 42. 3. Guaranteed by design, not tested in production. Doc ID 14611 Rev 7 85/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 42. I/O AC characteristics definition 90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out T 10% 50% 90% tr(I O)out Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 45). Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48. Symbol VIL(NRST)(1) NRST pin characteristics Parameter NRST Input low level voltage Conditions Min -0.5 2 200 VIN VSS 30 40 50 100 300 Typ Max 0.8 V VDD+0.5 mV k ns ns Unit VIH(NRST)(1) NRST Input high level voltage Vhys(NRST) RPU VF(NRST)(1) VNF(NRST)(1) NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 43. Recommended NRST pin protection VDD NRST(2) RPU Filter 0.1 F Internal Reset External reset circuit(1) STM32F10xxx ai14132c 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 48. Otherwise the reset will not be taken into account by the device. 86/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.15 TIM timer characteristics The parameters given in Table 49 are guaranteed by design. Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 49. Symbol tres(TIM) TIMx(1) characteristics Parameter Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected 13.9 0 0 fTIMxCLK/2 36 16 65536 910 65536 x 65536 fTIMxCLK = 72 MHz 59.6 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK s tTIMxCLK s fEXT ResTIM tCOUNTER tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. Doc ID 14611 Rev 7 87/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.16 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 10. The STM32F103xC, STM32F103xD and STM32F103xE performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 50. Refer also to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 50. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb I2C characteristics Standard mode I2C(1) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0(3) 1000 300 0.6 s 0.6 0.6 1.3 400 s s pF Max Min 1.3 s 0.6 100 0(4) 20 + 0.1Cb 900(3) 300 300 ns Max Fast mode I2C(1)(2) Unit 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 88/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Figure 44. I2C bus AC waveforms and measurement circuit VDD 4 .7 k I2C bus VDD 4 .7 k STM32F103xx SDA 100 SCL Electrical characteristics 100 S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART tr(SDA) tw(SCKL) tsu(SDA) th(SDA) S TOP tsu(STA:STO) tr(SCK) tf(SCK) tsu(STO) ai14149b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 51. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 300 200 100 50 20 0x801E 0x8028 0x803C 0x00B4 0x0168 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 14611 Rev 7 89/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 52. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) tsu(NSS)(2) th(NSS)(2) tw(SCKH) tw(SCKL)(2) tsu(MI) (2) tsu(SI)(2) th(MI) (2) (2) SPI characteristics(1) Parameter SPI clock frequency Slave mode SPI clock rise and fall time Capacitive load: C = 30 pF 30 4tPCLK 2tPCLK 50 5 5 5 4 0 2 3tPCLK 10 25 5 15 2 ns 60 18 8 70 ns % Conditions Master mode Min Max 18 MHz Unit SPI slave input clock duty Slave mode cycle NSS setup time NSS hold time SCK high and low time Slave mode Slave mode Master mode, fPCLK = 36 MHz, presc = 4 Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Data output disable time Data output valid time Data output valid time Data output hold time Master mode (after enable edge) Slave mode, fPCLK = 20 MHz Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) th(SI)(2) ta(SO)(2)(3) tdis(SO)(2)(4) tv(SO) (2)(1) tv(MO)(2)(1) th(SO)(2) th(MO) (2) 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 90/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Figure 45. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN th(SI) B I T1 IN Electrical characteristics th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) LSB OUT tv(SO) MS B O UT th(SO) BI T6 OUT tdis(SO) LSB IN ai14134c Figure 46. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 14611 Rev 7 91/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 47. SPI timing diagram - master mode(1) High NSS input tc(SCK) SCK Input SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTPUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 92/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 53. Symbol DuCy(SCK) Electrical characteristics I2S characteristics Parameter I2S slave input clock duty cycle I2S clock frequency Conditions Slave mode Master mode (data: 16 bits, Audio frequency = 48 kHz) Slave mode I2S clock rise and fall time WS valid time WS hold time WS setup time WS hold time CK high and low time Capacitive load CL = 50 pF Master mode I2S2 Master mode I2S3 Slave mode Slave mode Master fPCLK= 16 MHz, audio frequency = 48 kHz I2S2 Data input setup time Data input setup time Data input hold time Slave receiver Data output valid time Data output hold time Data output valid time Data output hold time Slave transmitter (after enable edge) Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) 0 11 3 0.5 18 Master receiver I2S3 Slave receiver Master receiver 6.5 1.5 0 0 4 0 312.5 345 2 3 2 Min 30 1.522 0 Max 70 1.525 MHz 6.5 8 ns Unit % fCK 1/tc(CK) tr(CK) tf(CK) tv(WS) (1) th(WS) (1) tsu(WS) th(WS) (1) (1) (1) tw(CKH) tw(CKL) (1) tsu(SD_MR) (1) tsu(SD_SR) (1) th(SD_MR)(1)(2) th(SD_SR) (1)(2) tv(SD_ST) (1)(2) th(SD_ST) (1) tv(SD_MT) (1)(2) th(SD_MT) (1) 1. Based on design simulation and/or characterization results, not tested in production. 2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. Doc ID 14611 Rev 7 93/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 48. I2S slave timing diagram (Philips protocol)(1) tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) WS input tsu(WS) SDtransmit LSB transmit(2) tsu(SD_SR) SDreceive LSB receive(2) MSB receive MSB transmit tv(SD_ST) Bitn transmit th(SD_SR) Bitn receive LSB receive th(SD_ST) LSB transmit tw(CKL) th(WS) ai14881b 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 49. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) tc(CK) CK output CPOL = 0 tw(CKH) CPOL = 1 tv(WS) WS output tv(SD_MT) SDtransmit LSB transmit(2) tsu(SD_MR) SDreceive LSB receive(2) MSB receive MSB transmit Bitn transmit th(SD_MR) Bitn receive LSB receive th(SD_MT) LSB transmit tw(CKL) th(WS) ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 94/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 54 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 50. SDIO high-speed mode tf tr tC tW(CKH) CK tOV D, CMD (output) tISU D, CMD (input) ai14887 tW(CKL) tOH tIH Figure 51. SD default mode CK tOVD D, CMD (output) tOHD ai14888 Doc ID 14611 Rev 7 95/123 Electrical characteristics Table 54. Symbol fPP tW(CKL) tW(CKH) tr tf STM32F103xC, STM32F103xD, STM32F103xE SD / MMC characteristics Parameter Clock frequency in data transfer mode Clock low time, fPP = 16 MHz Clock high time, fPP = 16 MHz Clock rise time Clock fall time Conditions CL 30 pF CL 30 pF CL 30 pF CL 30 pF CL 30 pF Min 0 32 31 ns 3.5 5 Max 48 Unit MHz CMD, D inputs (referenced to CK) tISU tIH Input setup time Input hold time CL 30 pF CL 30 pF 2 ns 0 CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV tOH Output valid time Output hold time CL 30 pF CL 30 pF 0.3 6 ns CMD, D outputs (referenced to CK) in SD default mode(1) tOVD tOHD Output valid default time Output hold default time CL 30 pF CL 30 pF 0.5 7 ns 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 55. USB startup time Parameter USB transceiver startup time Max 1 Unit s Symbol tSTARTUP(1) 1. Guaranteed by design, not tested in production. 96/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 56. Symbol Input levels VDD VDI (4) Electrical characteristics USB DC electrical characteristics Parameter Conditions Min.(1) Max.(1) Unit USB operating voltage(2) Differential input sensitivity I(USBDP, USBDM) 3.0(3) 0.2 0.8 1.3 3.6 V VCM(4) VSE(4) Differential common mode range Includes VDI range Single ended receiver threshold 2.5 2.0 V Output levels VOL VOH Static output level low Static output level high RL of 1.5 k to 3.6 V(5) RL of 15 k to VSS(5) 2.8 0.3 V 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by characterization, not tested in production. 5. RL is the load connected on the USB drivers Figure 52. USB timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines V CRS VS S tf tr ai14137 Table 57. USB: full-speed electrical characteristics Driver characteristics(1) Symbol tr tf trfm VCRS Parameter Rise time(2) Fall Time(2) Conditions CL = 50 pF CL = 50 pF tr/tf Min 4 4 90 1.3 Max 20 20 110 2.0 Unit ns ns % V Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.17 CAN (controller area network) interface Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). Doc ID 14611 Rev 7 97/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.18 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Note: Table 58. Symbol VDDA VREF+ IVREF fADC fS(2) fTRIG(2) VAIN RAIN(2) RADC(2) CADC(2) tCAL(2) tlat(2) tlatr(2) tS(2) tSTAB(2) tCONV(2) It is recommended to perform a calibration after each power-up. ADC characteristics Parameter Power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate External trigger frequency Conversion voltage range(3) External input impedance Sampling switch resistance Internal sample and hold capacitor Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) fADC = 14 MHz fADC = 14 MHz 5.9 83 fADC = 14 MHz 0.214 3(4) fADC = 14 MHz 0.143 2 fADC = 14 MHz 0.107 1.5 0 1 0 (4) Conditions Min 2.4 2.4 Typ Max 3.6 VDDA Unit V V A MHz MHz kHz 1/fADC V k k pF s 1/fADC s 1/fADC s 1/fADC s 1/fADC s s 1/fADC 160(1) 0.6 0.05 fADC = 14 MHz 220(1) 14 1 823 17 0 (VSSA or VREFtied to ground) See Equation 1 and Table 59 for details VREF+ 50 1 8 17.1 239.5 1 18 14 to 252 (tS for sampling +12.5 for successive approximation) 1. Based on characterization results, not tested in production. 2. Guaranteed by design, not tested in production. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 58. 98/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Equation 1: RAIN max formula TS R AIN ------------------------------------------------------------- - R ADC N+2 f ADC C ADC ln 2 Electrical characteristics The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 59. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (s) 0.11 0.54 0.96 2.04 2.96 3.96 5.11 17.1 0.4 5.9 11.4 25.2 37.2 50 NA NA RAIN max (k) 1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5 1. Guaranteed by design, not tested in production. Table 60. Symbol ET EO EG ED EL ADC accuracy - limited test conditions(1)(2) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration VREF+ = VDDA Typ 1.3 1 0.5 0.7 0.8 Max(3) 2 1.5 1.5 1 1.5 LSB Unit 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 3. Based on characterization, not tested in production. Doc ID 14611 Rev 7 99/123 Electrical characteristics Table 61. Symbol ET EO EG ED EL STM32F103xC, STM32F103xD, STM32F103xE ADC accuracy(1) (2)(3) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Test conditions Typ 2 1.5 1.5 1 1.5 Max(4) 5 2.5 3 2 3 LSB Unit 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 4. Based on characterization, not tested in production. Figure 53. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 5 6 7 4093 4094 4095 4096 VDDA ai14395b 100/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Figure 54. Typical connection diagram using the ADC VDD VT 0.6 V AINx Cparasitic VT 0.6 V IL1 A Electrical characteristics RAIN(1) STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) VAIN ai14150c 1. Refer to Table 58 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 55 or Figure 56, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 55. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F103xx VREF+ (see note 1) 1 F // 10 nF VDDA 1 F // 10 nF VSSA /VREF- (see note 1) ai14388b 1. VREF+ and VREF- inputs are available only on 100-pin packages. Doc ID 14611 Rev 7 101/123 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 56. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 F // 10 nF VREF-/VSSA (See note 1) ai14389 1. VREF+ and VREF- inputs are available only on 100-pin packages. 102/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.19 Table 62. Symbol VDDA VREF+ VSSA RLOAD(1) RO(1) DAC electrical specifications DAC characteristics Parameter Analog supply voltage Reference supply voltage Ground Min 2.4 2.4 0 Typ 3.6 3.6 0 Max Unit V V V k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V VREF+ must always be below VDDA Comments Resistive load with buffer ON 5 Impedance output with buffer OFF 15 k CLOAD(1) Capacitive load 50 pF DAC_OUT Lower DAC_OUT voltage min(1) with buffer ON DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) DAC_OUT Lower DAC_OUT voltage min(1) with buffer OFF DAC_OUT Higher DAC_OUT voltage with buffer OFF max(1) IDDVREF+ DAC DC current consumption in quiescent mode (Standby mode) 0.2 V VDDA - 0.2 0.5 V mV It gives the maximum output excursion of the DAC. VREF+ - 1LSB V With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Given for the DAC in 10-bit configuration Given for the DAC in 12-bit configuration Given for the DAC in 10-bit configuration Given for the DAC in 12-bit configuration 220 A 380 IDDA DAC DC current consumption in quiescent mode (Standby mode) A 480 A DNL(2) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) 0.5 LSB 2 1 LSB LSB INL(2) 4 LSB Doc ID 14611 Rev 7 103/123 Electrical characteristics Table 62. Symbol STM32F103xC, STM32F103xD, STM32F103xE DAC characteristics (continued) Parameter Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Min Typ 10 3 12 0.5 Max Unit mV LSB LSB % Comments Given for the DAC in 12-bit configuration Given for the DAC in 10-bit at VREF+ = 3.6 V Given for the DAC in 12-bit at VREF+ = 3.6 V Given for the DAC in 12bit configuration Offset(2) Gain error(2) Gain error Settling time (full scale: for a 10-bit input code transition (2) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value 1LSB Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) 3 4 s CLOAD 50 pF, RLOAD 5 k 1 MS/s CLOAD 50 pF, RLOAD 5 k CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. No RLOAD, CLOAD = 50 pF Wakeup time from off state tWAKEUP(2) (Setting the ENx bit in the DAC Control register) Power supply rejection ratio PSRR+ (1) (to VDDA) (static DC measurement 1. Guaranteed by design, not tested in production. 6.5 10 s -67 -40 dB 2. Guaranteed by characterization, not tested in production. Figure 57. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 104/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.20 Temperature sensor characteristics Table 63. Symbol TL(1) Avg_Slope V25 (1) (1) TS characteristics Parameter VSENSE linearity with temperature Average slope Voltage at 25 C Startup time ADC sampling time when reading the temperature 4.0 1.34 4 Min Typ 1 4.3 1.43 Max 2 4.6 1.52 10 17.1 Unit C mV/C V s s tSTART(2) TS_temp(3)(2) 1. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Doc ID 14611 Rev 7 105/123 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE 6 6.1 Package characteristics Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad Dsm Solder paste Dpad Dsm 0.37 mm 0.52 mm typ. (depends on solder mask registration tolerance 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print ai15469 106/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 59. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline C Seating plane A2 A4 A3 B D D1 e M F F A A A1 ddd C E1 E e Ob (144 balls) Ball A1 O eee M C A O fff M C B X3_ME 1. Drawing is not to scale. Table 64. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data millimeters inches(1) Max 1.70 0.21 1.07 0.27 0.85 0.35 9.85 0.40 10.00 8.80 9.85 10.00 8.80 0.80 0.60 0.10 0.15 0.08 10.15 0.3878 0.45 10.15 0.0138 0.3878 0.0157 0.3937 0.3465 0.3937 0.3465 0.0315 0.0236 0.0039 0.0059 0.0031 0.3996 0.0083 0.0421 0.0106 0.0335 0.0177 0.3996 Typ Min Max 0.0669 Symbol Min A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff Typ 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14611 Rev 7 107/123 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 60. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline 1. Drawing is not to scale. Table 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data millimeters inches(1) Max 1.700 0.270 1.085 0.30 0.80 0.45 9.85 0.50 10.00 7.20 9.85 10.00 7.20 0.80 1.40 0.12 0.15 0.08 10.15 0.3878 0.55 10.15 0.0177 0.3878 0.0197 0.3937 0.2835 0.3937 0.2835 0.0315 0.0551 0.0047 0.0059 0.0031 0.3996 0.0106 0.0427 0.0118 0.0315 0.0217 0.3996 Min Typ Max 0.0669 Symbol Min A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff Typ 1. Values in inches are converted from mm and rounded to 4 decimal digits. 108/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 61. WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline e1 A1 ball corner D A e A1 ball corner e H Detail A B C D E e1 E F Notch G L aaa L Wafer back side Ball Side view A2 A 8 7 6 5 4 Ball side 3 H F Marking area G 2 1 eee A1 b Seating plane (see note 2) Detail A rotated 90 CR_ME 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the ball. Table 66. WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data millimeters inches(1) Max 0.635 0.255 0.380 0.350 Min 0.0211 0.0081 0.0130 0.0114 Typ 0.0230 0.0091 0.0140 0.0126 0.0197 0.1378 0.0176 0.0190 4.486 4.415 0.1750 0.1722 0.1758 0.1730 0.0098 0.0079 0.0020 0.0039 64 0.1766 0.1738 Max 0.0250 0.0100 0.0150 0.0138 Symbol Min A A1 A2 b (2) Typ 0.585 0.230 0.355 0.320 0.500 3.500 0.447 0.483 0.535 0.205 0.330 0.290 e e1 F G D E H L eee aaa Number of balls 4.446 4.375 4.466 4.395 0.250 0.200 0.05 0.10 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum ball diameter parallel to primary datum Z. Doc ID 14611 Rev 7 109/123 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 62. Recommended PCB design rules (0.5 mm pitch BGA) Dpad Dsm Solder paste Dpad Dsm 0.37 mm 0.52 mm typ. (depends on solder mask registration tolerance 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print ai15469 110/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 63. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline(1) Seating plane C Figure 64. Recommended footprint(1)(2) A A2 A1 ccc C b c 0.25 mm gage plane D D1 D3 A1 73 72 0.5 109 108 73 1.35 0.35 72 k L L1 19.9 17.85 22.6 108 109 144 37 E1 E3 E 1 19.9 22.6 36 ai149 144 37 1 36 Pin 1 identification e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 67. Symbol LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.60 0.05 1.35 0.17 0.09 21.80 19.80 22.00 20.00 17.50 21.80 19.80 22.00 20.00 17.50 0.50 0.45 0.60 1.00 0 3.5 0.08 7 0 0.75 0.0177 22.20 20.20 0.8583 0.7795 1.40 0.22 0.15 1.45 0.27 0.20 22.20 20.20 0.002 0.0531 0.0067 0.0035 0.8583 0.7795 0.8661 0.7874 0.689 0.8661 0.7874 0.689 0.0197 0.0236 0.0394 3.5 0.0031 7 0.0295 0.874 0.7953 0.0551 0.0087 Min inches(1) Typ Max 0.063 0.0059 0.0571 0.0106 0.0079 0.874 0.7953 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14611 Rev 7 111/123 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 66. Recommended footprint(1)(2) Figure 65. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE k 75 D D1 D3 75 76 51 51 L L1 C 50 76 0.5 50 0.3 16.7 14.3 b E3 E1 E 100 100 26 25 26 1.2 Pin 1 1 identification e 1 ccc C 25 12.3 A1 A2 A SEATING PLANE C 1L_ME 16.7 ai14906b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 68. Symbol LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.60 0.05 1.35 0.17 0.09 15.80 13.80 16.00 14.00 12.00 15.80 13.80 16.00 14.00 12.00 0.50 0.45 0.60 1.00 0 3.5 0.08 7 0 0.75 0.0177 16.20 14.20 0.622 0.5433 1.40 0.22 0.15 1.45 0.27 0.20 16.20 14.20 0.002 0.0531 0.0067 0.0035 0.622 0.5433 0.6299 0.5512 0.4724 0.6299 0.5512 0.4724 0.0197 0.0236 0.0394 3.5 0.0031 7 0.0295 0.6378 0.5591 0.0551 0.0087 Min inches(1) Typ Max 0.063 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. 112/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 68. Recommended footprint(1)(2) Figure 67. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline(1) A A2 48 33 0.3 A1 49 0.5 32 E E1 b 12.7 10.3 e 10.3 64 17 1.2 1 16 7.8 12.7 ai14398b D1 D L1 L c ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 69. Symbol LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 A A1 A2 b c D D1 E E1 e L L1 N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14611 Rev 7 113/123 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE 6.2 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 42. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 70. Symbol Package thermal characteristics Parameter Thermal resistance junction-ambient LFBGA144 - 10 x 10 mm / 0.8 mm pitch Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm / 0.8 mm pitch Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch Thermal resistance junction-ambient WLCSP64 Value 40 30 40 C/W 46 45 50 Unit JA 6.2.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 114/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 71: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xC, STM32F103xD and STM32F103xE at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 70 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 82 C + (46 C/W x 447 mW) = 82 C + 20.6 C = 102.6 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 71: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Doc ID 14611 Rev 7 115/123 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Using the values obtained in Table 70 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 115 C + (46 C/W x 134 mW) = 115 C + 6.2 C = 121.2 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 71: Ordering information scheme). Figure 69. LQFP100 PD max vs. TA 700 600 PD (mW) 500 400 300 200 100 0 65 75 85 95 105 115 125 135 Suffix 6 Suffix 7 TA (C) 116/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Part numbering 7 Part numbering Table 71. Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package H = BGA T = LQFP Y = WLCSP64 Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and real Ordering information scheme STM32 F 103 R C T 6 xxx For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 14611 Rev 7 117/123 Revision history STM32F103xC, STM32F103xD, STM32F103xE 8 Revision history Table 72. Date 07-Apr-2008 Document revision history Revision 1 Initial release. Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 2 added in Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts on page 11. LQPF100/BGA100 column added to Table 6: FSMC pin definition on page 36. Values and Figures added to Maximum current consumption on page 44 (see Table 14, Table 15, Table 16 and Table 17 and see Figure 14, Figure 15, Figure 17, Figure 18 and Figure 19). Values added to Typical current consumption on page 50 (see Table 18, Table 19 and Table 20). Table 19: Typical current consumption in Standby mode removed. Note 4 and Note 1 added to Table 56: USB DC electrical characteristics and Table 57: USB: full-speed electrical characteristics on page 97, respectively. VUSB added to Table 56: USB DC electrical characteristics on page 97. Figure 64: Recommended footprint(1) on page 111 corrected. Equation 1 corrected. Figure 69: LQFP100 PD max vs. TA on page 116 modified. Tolerance values corrected in Table 64: LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data on page 107. Changes 22-May-2008 2 118/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 72. Date Revision history Document revision history Revision Changes Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 15 modified. Number of complementary channels corrected in Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram. Power supply supervisor on page 17 modified and VDDA added to Table 10: General operating conditions on page 42. Table notes revised in Section 5: Electrical characteristics. Capacitance modified in Figure 12: Power supply scheme on page 40. Table 51: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) updated. Table 52: SPI characteristics modified, th(NSS) modified in Figure 45: SPI timing diagram - slave mode and CPHA = 0 on page 91. Minimum SDA and SCL fall time value for Fast mode removed from Table 50: I2C characteristics on page 88, note 1 modified. IDD_VBAT values and some IDD values with regulator in run mode added to Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 48. Table 30: Flash memory endurance and data retention on page 61 updated. tsu(NSS) modified in Table 52: SPI characteristics on page 90. EO corrected in Table 61: ADC accuracy on page 100. Figure 54: Typical connection diagram using the ADC on page 101 and note below corrected. Typical TS_temp value removed from Table 63: TS characteristics on page 105. Section 6.1: Package mechanical data on page 106 updated. Small text changes. 21-Jul-2008 3 Doc ID 14611 Rev 7 119/123 Revision history Table 72. Date STM32F103xC, STM32F103xD, STM32F103xE Document revision history Revision Changes Timers specified on page 1 (motor control capability mentioned). Section 2.2: Full compatibility throughout the family updated. Table 4: High-density timer feature comparison added. General-purpose timers (TIMx) and Advanced-control timers (TIM1 and TIM8) on page 19 updated. Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram modified. Note 10 added, main function after reset and Note 5 on page 35 updated in Table 5: High-density STM32F103xx pin definitions. Note 2 modified below Table 7: Voltage characteristics on page 41, |VDDx| min and |VDDx| min removed. Note 2 and PD values for LQFP144 and LFBGA144 packages added to Table 10: General operating conditions on page 42. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 44. Max values at TA = 85 C and TA = 105 C updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 48. Section 5.3.10: FSMC characteristics on page 61 updated. Data added to Table 42: EMI characteristics on page 81. IVREF added to Table 58: ADC characteristics on page 98. Table 70: Package thermal characteristics on page 114 updated. Small text changes. 12-Dec-2008 4 120/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Table 72. Date Revision history Document revision history Revision Changes I/O information clarified on page 1. Figure 4: STM32F103xC and STM32F103xE performance line BGA100 ballout corrected. I/O information clarified on page 1. In Table 5: High-density STM32F103xx pin definitions: - I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15 updated - PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column PG14 pin description modified in Table 6: FSMC pin definition. Figure 9: Memory map on page 38 modified. Note modified in Table 14: Maximum current consumption in Run mode, code with data processing running from Flash and Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 17, Figure 18 and Figure 19 show typical curves (titles changed). Table 21: High-speed external user clock characteristics and Table 22: Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 25: HSI oscillator characteristics. FSMC configuration modified for Asynchronous waveforms and timings. Notes modified below Figure 24: Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms and Figure 25: Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms. tw(NADV) values modified in Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings and Table 34: Asynchronous multiplexed PSRAM/NOR write timings. th(Data_NWE) modified in Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings In Table 36: Synchronous multiplexed PSRAM write timings and Table 38: Synchronous non-multiplexed PSRAM write timings: - tv(Data-CLK) renamed as td(CLKL-Data) - td(CLKL-Data) min value removed and max value added - th(CLKL-DV) / th(CLKL-ADV) removed Figure 28: Synchronous multiplexed NOR/PSRAM read timings, Figure 29: Synchronous multiplexed PSRAM write timings and Figure 31: Synchronous non-multiplexed PSRAM write timings modified. Figure 48: I2S slave timing diagram (Philips protocol)(1) and Figure 49: I2S master timing diagram (Philips protocol)(1) modified. WLCSP64 package added (see Figure 8: STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side, Table 5: High-density STM32F103xx pin definitions, Figure 61: WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline and Table 66: WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data). Small text changes. 30-Mar-2009 5 Doc ID 14611 Rev 7 121/123 Revision history Table 72. Date STM32F103xC, STM32F103xD, STM32F103xE Document revision history Revision Changes Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram updated. Note 5 updated and Note 4 added in Table 5: High-density STM32F103xx pin definitions. VRERINT and TCoeff added to Table 13: Embedded internal reference voltage. Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM modified. fHSE_ext min modified in Table 21: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Note 1 modified below Figure 22: Typical application with an 8 MHz crystal. Table 25: HSI oscillator characteristics modified. Conditions removed from Table 27: Low-power mode wakeup timings. Jitter added to Table 28: PLL characteristics. Figure 43: Recommended NRST pin protection modified. In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings: th(BL_NOE) and th(A_NOE) modified. In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings: th(A_NWE) and th(Data_NWE) modified. In Table 33: Asynchronous multiplexed PSRAM/NOR read timings: th(AD_NADV) and th(A_NOE) modified. In Table 34: Asynchronous multiplexed PSRAM/NOR write timings: th(A_NWE) modified. In Table 35: Synchronous multiplexed NOR/PSRAM read timings: th(CLKH-NWAITV) modified. In Table 40: Switching characteristics for NAND Flash read and write cycles: th(NOE-D) modified. Table 52: SPI characteristics modified. Values added to Table 53: I2S characteristics and Table 54: SD / MMC characteristics. CADC and RAIN parameters modified in Table 58: ADC characteristics. RAIN max values modified in Table 59: RAIN max for fADC = 14 MHz. Table 62: DAC characteristics modified. Figure 57: 12-bit buffered /nonbuffered DAC added. Figure 60: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline and Table 65: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data updated. Number of DACs corrected in Table 3: STM32F103xx family. IDD_VBAT updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes. Figure 16: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.11: EMC characteristics on page 80. Table 62: DAC characteristics modified. Small text changes. 21-Jul-2009 6 24-Sep-2009 7 122/123 Doc ID 14611 Rev 7 STM32F103xC, STM32F103xD, STM32F103xE Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 14611 Rev 7 123/123 |
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